VLSI System Design (VSD) — Builders — IndiaBUILD

The registry · Builder record

R&D

Assessed stage · IndiaBUILD, from evidence

—

Claimed stage · the builder's own words

01

Capabilities attempted

00

Dated updates

Attempting

Highlight

Full-flow EDA toolchain (RTL to GDSII)

No capability software

Evidence

independently corroborable, distinct from claims

1 · [demo] Successfully demonstrated working open-source RTL-to-GDS flow on SCL 180nm process node; enables designers to take design from RTL to GDSII using open-source EDA tools mapped to Indian PDK
2 · [milestone] Trains 28,700+ students globally on open-source EDA/hardware through online courses; co-founder worked with IIT Madras and IIT Guwahati on open-source projects

Dated updates

No updates recorded yet.