Advanced process design kit and EDA toolchain

Three companies — Cadence, Synopsys and Siemens EDA — control roughly 80% of the electronic design automation tools used at semiconductor companies worldwide. Every chip designed in India today is drawn with software owned in the United States or South Korea. As of 2026, India imports 100% of its CMOS EDA tools and advanced process design kits.

A process design kit is the bridge between a design idea and a specific fab. It is a set of files a foundry supplies to model its own manufacturing process: design rules, SPICE transistor models, standard cell libraries, layout information. Without one, a designer cannot know whether a circuit will actually work when etched into silicon. PDKs are foundry-specific by nature — they encode the physics of one company's process at one technology node — which makes them monopolies that no outside party can replicate. The EDA toolchain that reads them is equally entrenched: Cadence's Virtuoso for analog design, Synopsys's Design Compiler and VCS simulators, Siemens's Tessent for design-for-test, each refined over decades.

India's current position is one of access, not ownership. The Centre for Development of Advanced Computing runs the ChipIN Centre and a national EDA grid that gives subsidised access to Cadence, Synopsys and Siemens tools. As of January 2026, 95 startups and 305 academic institutions had used the grid for more than 54 million cumulative hours. Under the Design Linked Incentive scheme, supported firms had developed over 140 reusable IP cores, completed 16 tape-outs and fabricated six chips. The one indigenous PDK output arrived on 24 April 2026, when IIT Madras launched a Silicon Photonics PDK with over 50 verified components — a domain-specific kit for photonic integrated circuits, fabricated through SilTerra Malaysia, not a general-purpose CMOS toolchain.

The gap persists because a PDK cannot exist without the foundry it describes. India's Semiconductor Laboratory in Chandigarh runs an 8-inch fab at the 180nm node; there is no advanced CMOS fabrication below 65nm on Indian soil. Standard cell libraries and SPICE compact device models — the raw ingredients of a PDK — are effectively absent. The design ecosystem, taught on licensed vendor tools at IIT Bombay, Hyderabad and Jammu, builds skills but no indigenous software.

Closing it would mean advancing on two fronts at once: functional foundries at competitive nodes to generate PDKs, and the sustained toolchain investment beneath them. The IIT Madras photonics kit shows the design capability exists. The silicon underneath it does not yet.