Advanced transistor architecture (FinFET/GAA)

Every advanced chip on Earth — the processors in phones, data centres, and AI accelerators — runs on one of two transistor shapes: the FinFET or its successor, the gate-all-around (GAA) nanosheet. As of 2026, India produces neither, at any scale. Import dependence is complete.

The difficulty is real and it compounds. A FinFET raises the transistor channel into a vertical fin so the gate can grip it on three sides; GAA goes further, stacking ultra-thin nanosheets and wrapping the gate 360 degrees around each one. Building this means creating those stacked nanosheets precisely, then depositing gate material inside microscopic gaps using novel etching techniques — work that only exists at sub-3nm process nodes. Intel first commercialised FinFET at 22nm in 2011; TSMC and Samsung followed at 16 and 14nm. Samsung put GAA into production at 3nm in 2022 and shipped its first consumer GAA chip, the Exynos W1000, in 2024. Only three nations hold the capability: Taiwan, South Korea, and the United States.

India's honest status is R&D. IISc's Centre for Nano Science and Engineering developed methods in 2018 for improving the reliability of sub-14nm FinFET system-on-chips, and received Rs 3,000 crore from DRDO's Solid State Physics Laboratory in 2017 for a lab-scale foundry fabricating GaN transistors on silicon. IIT Bombay's Centre of Excellence in Nanoelectronics runs a lab-scale facility for CMOS device research. These are genuine capabilities, but they are laboratory demonstrations, not foundries.

The gap persists because a transistor architecture sits atop a deep stack of foundational processes India does not yet possess. Sub-3nm patterning needs High-NA EUV lithography; nanosheet GAA needs atomic layer deposition, silicon-germanium epitaxy, and computational lithography with advanced photomasks. India has no sub-14nm validated process design kit. Its first fabs point elsewhere: the Tata-PSMC plant in Dholera targets 28-110nm using mature planar CMOS, explicitly not FinFET. Of the ten semiconductor projects approved as of March 2026, only two are fabrication plants, both at mature nodes. The US-India ITSI partnership of September 2024 focuses on assembly, testing, and packaging — the final step, not the front end.

What it would take is the whole underlying stack, not a single leap. The materials work has begun: IIT-Mandi and others received MeitY funding for sub-10nm photoresist development. Advanced transistor production would follow from EUV lithography, ALD, SiGe epitaxy, and a validated PDK maturing together — and from a fab built to receive them.