Analog/mixed-signal EDA tools

Every custom analog integrated circuit designed in India — every power management chip, RF front-end, and sensor interface — is drawn, simulated, and verified on software written by three foreign companies. As of 2025, one hundred percent of the commercial analog and mixed-signal EDA (electronic design automation) tools used in the country are sourced from Synopsys, Cadence, and Siemens EDA. No indigenous alternative exists at any stage.

Analog EDA is one of the hardest corners of the software industry to enter, and its economics explain why. The analog and mixed-signal segment is a small slice of the overall EDA market, yet it demands the deepest tools: SPICE simulation engines, device models accurate to the transistor, electromagnetic simulation for RF, and co-simulation platforms that verify analog and digital blocks together. The three vendors control roughly 74 percent of the global EDA market — Synopsys 31 percent, Cadence 30 percent, Siemens EDA 13 percent. That dominance is protected by extreme lock-in: design flows are sequential, so switching one tool forces the re-running of place-and-route, signoff, and physical verification down the chain.

India's official response has been access, not construction. The ChipIN Centre at C-DAC provides centralised, subsidised access to commercial tools from Cadence, Synopsys, Siemens EDA, and Keysight to over 300 academic institutions and more than 95 startups. This solves a real problem — the multi-million-dollar annual cost of these tool suites has long been the primary barrier for new fabless design firms. But it is licensed foreign software. ChipIN's own training programmes teach schematic-to-GDSII analog design using Cadence and Siemens tools as the standard. The Design Linked Incentive scheme had approved 23 chip design projects by January 2026, all built on imported tools.

The gap persists because the foundations beneath an EDA suite are themselves import-dependent. The critical dependencies — SPICE engines, device modelling and TCAD, electromagnetic simulation, mixed-signal verification — are all capabilities where India is not competitive. Most decisive of all, advanced-node process technology at 28nm and below, which modern analog EDA must model rule-by-rule, is absent domestically. An indigenous tool cannot outrun the process nodes it is meant to design for.

What it would take is a stack, not a product: competitive SPICE and device-modelling kernels, foundry-specific process design kits, and verification platforms that match a bar now being raised by AI-driven tools like Synopsys' ASO.ai. India already employs close to 20 percent of the world's chip design workforce. The talent operates the tools; building them is the next climb.