SiC wafer slicing and polishing

India lacks indigenous SiC wafer slicing and polishing capability; DRDO achieved 4-inch wafer growth in 2024 but full manufacturing (slicing, grinding, CMP) remains undemonstrated at production scale.

SiC wafer slicing and polishing
India's statusEmerging since 2026
Criticalitycritical
Import dependence90% of wide-bandgap semiconductors imported (2025)
Global makers5
United States · Japan · South Korea · China · Europe
Typeprocess
SectorSemiconductors
Rests on7 capabilities
Deep-red gaps1
VerificationMachine-checked
Revised2026-07-15

1The gap

Ninety per cent of the wide-bandgap semiconductor chips India uses in 2025 are imported. Silicon carbide sits at the heart of that dependence — the material that gates next-generation power electronics for electric vehicles, renewables and defence. And the step that turns a grown SiC crystal into a usable wafer is one of the hardest in the entire chain.

SiC is second in hardness only to diamond. That single property makes every downstream step difficult. Slicing an ingot requires diamond wire sawing with precise kerf control and cooling to limit subsurface damage. Polishing it is far harder than polishing silicon: SiC's chemical inertness and strong covalent bonding defeat conventional mechanical methods, leaving scratches and hidden damage. The finishing step, chemical mechanical polishing, must combine chemical surface modification with mechanical abrasion to reach the required smoothness. Advanced CMP that achieved sub-2-nanometre roughness in 2024 lifted epitaxy yield by 18 per cent — a measure of how tightly surface quality governs everything after it.

Only a handful of nations do this at scale. The five largest suppliers — Wolfspeed, Coherent, STMicroelectronics, ROHM and SK Siltron — controlled about half of global capacity in 2025.

Where India stands is early but real. DRDO's Solid State Physics Laboratory produced indigenous 4-inch SiC wafers and fabricated GaN HEMTs up to 150 watts in 2024 — a laboratory demonstration, not production. Several commercial projects have followed. RIR Power Electronics broke ground on a ₹618-crore facility in Bhubaneswar in September 2024, with Phase 1 epitaxy production expected by December 2025. Under India Semiconductor Mission 2.0, approved in August 2025, SiCSem of Chennai partnered with Scotland's Clas-SiC Wafer Fab for a Bhubaneswar plant rated at 60,000 wafers a year, expected operational in 2027–2028. Indichip Semiconductors and Japan's Yitoa Micro Technology announced a ₹14,000-crore fab in Kurnool in January 2025, still pre-construction.

No operational end-to-end slicing-and-polishing line has yet been reported in India.

The gap persists because the capability is a sequence, not a single machine. It rests on SiC bulk crystal growth upstream — growth quality determines slicing yield — and on diamond wire saws, lapping and grinding equipment, CMP tools and consumables, metrology, and SiC-specific process control. Each is a distinct competence, and the material's hardness forces custom recipes at every stage.

3The builders

Stage = IndiaBUILD assessment from evidence
01
Assessed · Limited production claims: limited production
02
Assessed · Prototype claims: testing
03
Assessed · R&D claims: —
04
Assessed · Study claims: —

4What it would take

Closing it means converting these announced fabs into demonstrated production, mastering the full slice-grind-polish sequence, and building the domestic crystal growth and consumables base beneath it. The projects exist; the demonstrated line does not yet.

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