Can India develop a full-flow EDA toolchain (RTL to GDSII)?

More than 20% of the world's semiconductor design engineers work in India. Yet as of 2025, India accounts for roughly 8% of the Asia-Pacific market for the software those engineers use — and for production-scale chip design, that software is 100% imported.

The tools in question are the electronic design automation (EDA) toolchain: the software that carries a chip from RTL — the register-transfer-level code that describes what a circuit should do — all the way to GDSII, the layout file a foundry uses to manufacture it. In between sit logic synthesis, place-and-route, static timing analysis, and physical verification, each a critical stage with no room for error before tapeout.

This is genuinely hard because the toolchain is a single unbroken chain: a gap at any stage breaks the whole flow. At advanced nodes the burden compounds — design-rule checking produces roughly ten times the checks at 7nm that it does at older nodes. The global market reflects this difficulty. Synopsys, Cadence, and Siemens together command an estimated 60–70% of EDA software revenue, a concentration held by builders in only the United States, Germany, and Japan.

India's current position is one of access, not ownership. C-DAC operates the national EDA grid through its ChipIN Centre, giving 95 companies access to industry-grade tools; cumulative usage passed 54 million hours by January 2026. The India Semiconductor Mission has approved over $10 billion in incentives, and the Design Linked Incentive scheme supports 24 design projects and access for 72-plus companies. But these are imported proprietary platforms. Indigenous work sits at the research edge: VLSI System Design has demonstrated a working open-source RTL-to-GDS flow on the domestic SCL 180nm process node, mapping open-source tools onto an Indian PDK, and IIT Madras has launched a silicon photonics PDK with 50-plus pre-verified components. Both are real; neither is production-grade at competitive nodes.

The gap persists because the toolchain rests on foundational layers India has only begun to build. Process design kits and standard cell libraries — the foundry-specific rule sets and pre-designed logic cells every stage depends on — remain emerging, and India's PDK coverage extends to legacy nodes like 180nm and 130nm. Without mature foundations, the tools above them cannot reach production maturity.

Closing the gap would mean building indigenous synthesis, place-and-route, timing, and verification tools that operate on domestic PDKs at competitive nodes — moving from demonstrated open-source flows on 180nm toward production-grade coverage. The ecosystem infrastructure exists; the tools themselves do not yet.